1. Field of the Invention
This invention generally relates to a digital type frequency relay for use in the protection of electric power transmission lines.
2. Description of the Prior Art
The frequency of an electric power transmission line is always maintained at a constant frequency. But in case the relationship between the quantity of generated electric power and the quantity of consumed electric power in the electric power transmission line is fairly unbalanced by a fault of the transmission line, the frequency can rise or fall accordingly.
If the frequency varies above or below a predetermined frequency, it is necessary to detect the fault by a frequency relay, and to carry out suitable controls, for example separating the transmission line with a fault from the normal transmission line, limiting the generated electric power, or limiting the consumed electric power.
A known digital type frequency relay is constituted to measure the period of the transmission line voltage in comparison with a steady high frequency signal generated by a crystal oscillator, etc., as a reference, whereby the actual frequency is detected by converting the decreasing or increasing period into a rising or falling frequency.
FIG. 1 shows a block diagram illustrating one example of a conventional digital type frequency relay. PT represents an auxiliary potential transformer which converts the line voltage to a suitable voltage level to be able to match the relay. BF represents a rectangular wave converting circuit which converts the sine wave from the potential transformer PT to the rectangular wave. DIV represents a divider circuit which divide the rectangular wave from the converting circuit to the period of 1/2.multidot.m(m=1, 2, 3 . . . ). The reason to provide this divider circuit is to accurately measure the period even when the input sine wave is biased to either a positive sign or a negative sign.
OSC represents an oscillator which oscillates at a reference frequency f.sub.OSC to measure the output period from the divider circuit DIV. AND represents a logical product circuit which receives the outputs of the divider circuit DIV and the oscillator OSC.
C represents a pulse counter which counts the number of pulses from the logical product circuit AND and has a reset terminal to clear the state of the counter C. SET represents a setter which sets a setting value. COM represents a comparator which compares the output of the pulse counter C with the setting value of setter SET.
TI represents a discriminator which judges the output of the discriminator TI on receiving a judging pulse explained hereinafter.
CC represents a controlling circuit which generates a clear pulse (CP) to be transmitted to the pulse counter C and a judging pulse JP to be transmitted to the discriminator TI.
One example of the detailed controlling circuit CC is constituted as shown in FIG. 2.
In the FIG. 2, the output of the divider circuit DIV is supplied to a first OFF time delay device TDD.sub.1 to delay for a predetermined time. The output of the first OFF time delay device TDD is supplied to a second OFF delay device TDD.sub.2 to delay for a predetermined time.
A first pulse generator PG.sub.1, connected with the output of the first time delay device TDD.sub.1, produces a judging pulse JP to be transmitted to the discriminator TI when the output of the first time delay device falls.
A second pulse generator PG.sub.2, connected with the output of the second time delay device TDD.sub.2, produces a clear pulse CP to be transmitted to the pulse counter C when the output of the second time delay device falls.
The waveforms of each portion of the digital type frequency relay shown in FIG. 1 are shown in Figure 3. The operation of the conventional digital type relay is explained in reference to FIG. 3.
The output of the divider circuit DIV is a waveform with a 50% duty cycle (mark/space ratio=1) and a period corresponding to the number of the periods of m cycles from the line voltage (potential transformer output), where m=1 as shown.
The pulse counter C counts the number of the reference clock signal generated by the oscillator OSC, while the output of the divider circuit is at the logic "1".
The counted value is compared with the setting value from the setter SET at the comparator COM.
In this relay, for example, an under frequency relay, the discriminator TI is set at a logic "1" on receiving the judging pulse JP when the counted value is larger than the setting value. Moreover, in order to continuously repeat measuring the period, the pulse counter C is initialized or cleared by a clear pulse CP generated from the controlling circuit after generation of the judging pulse JP.
As described above, in the conventional digital type frequency relay the judging pulse JP periodically generates one pulse every two m cycles (m=1, 2, 3, . . . ) and the judging of the operation is carried out.
However, this is a principal factor in producing the operating time error in the frequency relay, as explained hereinafter. For convenience's sake of the explanation, the under-frequency relay is explained below.
Referring to FIG. 3, again, the output of the discriminator TI represents the "operate" logic level at time t.sub.4, but in order to judge the operation of the relay at time t.sub.4, the frequency must change to less than the set frequency threshold before time t.sub.3, because the judging operation is carried out based on the counting result of pulse counter C which counts during one cycle commencing from time t.sub.3.
On the other hand, in case the frequency is less than the set frequency threshold before time t.sub.1, the output of the discriminator TI represents the "operate" level at time t.sub.2 based on the counting result of the pulse counter C which counts during one cycle commencing from time t.sub.1.
Accordingly, the output of the discriminator TI represents the "operate" output level so that the frequency must change less the set frequency threshold at a time t (t.sub.1 &lt;t&lt;t.sub.3).
Turning now to another consideration, in the time when the discriminator TI outputs the "operate" logic level after the frequency changes less than the set frequency threshold, i.e. the operating conditions are met, the operating time during the period (t.sub.3 -t.sub.1), i.e. substantially two m cycles, is not consistent in the principle.
Typically, the number of periods m to be measured is minimized in order to reduce the delay till operating time.
However, even if the number m is set to a numeral one, the delay of the operating time of substantially two cycles exists in principle.
Especially, in case that the system detects the changing rate of the frequency using two frequency relays and executes the protection of the power line, it is impossible to ignore the delay of operating time of two frequency relays.
It is, for instance, assumed that if the frequency of the power line falls to a value 0.5 Hz less than a rated frequency, this is to be detected.
Such a system is shown in FIG. 4. A first under-frequency relay UF.sub.1 is set to operating frequency F.sub.1 Hz is connected to one input terminal of an inhibit circuit INHIBIT through a time delay circuit TDE having a delay time of 0.2 seconds. A second under-frequency relay UF.sub.2 set to operating frequency f.sub.2 (f.sub.1 -0.5)Hz is connected to another input terminal of the inhibit circuit INHIBIT.
The inhibit circuit INHIBIT serves to block the output thereof when the output of the time delay circuit TDE is at an "operating" logic level.
The operation of the system shown in FIG. 4 is explained. In the event that after the first under frequency relay UF.sub.1 generates an "operating" logic level output, the second under frequency relay UF.sub.2 does likewise within 0.2 seconds, the output to be protected from inhibit circuit INHIBIT is generated because the second under frequency relay UF.sub.2 outputs before the inhibit conditions of the inhibit circuit are met.
It is therefore assumed that in this system the time to be detected is .DELTA.T seconds and the falling frequency deviation is .DELTA.F Hz, the output to be protected is generated under the following condition: ##EQU1##
Since the delay of substantially two cycles operating time in principle in the conventional frequency relay, as described above, exists, the influence of the delay is explained as follows:
If it is assumed the operating time of the relay is 100 milli-seconds, it should be understood that the scope of the delay of operating time is 40 milli-seconds (2 cycle.times.20 milli-seconds (1/50 Hz)) and a relatively maximum operating time difference, 80 milli-seconds (2.times.40 milli-seconds) between two relays exists. This means the error of the operating time of the system shown in FIG. 4 is as follows: ##EQU2##
Therefore, the system shown in FIG. 4 can be always operated if the changing rate of the frequency is larger than 3.13 Hz/sec, but the system can be not always operated when the changing rate varies in the range from 2.08 Hz/sec to 3.13 Hz/sec.
The system shown in FIG. 4 is intended always to be able to operate when the changing rate of the frequency is larger than 2.5 Hz/sec and always not to be able to operate when the changing rate is equal to and less than 2.5 Hz/sec.
However, as described above, an indefinite condition of the detecting sensitivity presents a limitation for executing the protection of the power line.